I recently spoke with Todd Westerhoff, product marketing manager for signal integrity software tools at Siemens. We discussed a new capability called HyperLynx Apps that offers a new take on traditional signal and power integrity analysis, and how that fits in with the Siemens plan to put SI and PI tools into the hands of more designers early in the design cycle.

Nolan Johnson: Todd, I understand there’s something new with HyperLynx.

Todd Westerhoff: That’s right. With HyperLynx our focus has always been about making signal and power integrity analysis accessible to a wider audience. Most SI/PI analysis today is performed by experts—people who do that analysis as their primary job. But there just aren’t enough SI/PI experts available to meet demand, and the problem is getting worse. We think it’s time to start looking at the problem differently.

I read a study from Semiconductor Engineering stating that the primary staffing problem electronics companies have is electrical engineers—they just can’t find enough of them, and it’s impacting project schedules. That study was pre-COVID, before the current exodus of experienced talent, and they were referring to general EEs, not SI/PI experts, who are much rarer. We recently searched LinkedIn for jobs relating to signal integrity and found over 2,000 jobs worldwide. Then we ran a more targeted search with just five companies with the acronym AMIGA—Apple, Microsoft, Intel, Google, and Amazon, and only in the United States. That focused search still listed 321 jobs­.

That means it’s a great time to be a signal integrity expert, but it’s terrible time to try to hire one. We’ve been talking about the “expert crunch” and how it hasn’t been getting any better for a while now; we think it’s time to think about how we can approach analysis differently. This requires a new vision for how high-speed systems should be designed and verified.

Johnson: Do you all believe the high-speed system design methodology needs to change?

Westerhoff: Yes, because we need to change the way we look at the problem. Let’s take a broad perspective: The classic definition of “high-speed” relates a signal’s edge rate to the electrical delay of the net. It defines the point at which you must pay attention to how you lay out that net. Simply put, if you have to pay attention to how you route it, it’s “high-speed.”

The challenge is that by today’s standards, everything is high speed. Using modern devices and typical board materials, the longest a net can be before it runs into “high-speed” issues is about one-quarter inch, and basically everything is longer than that. That doesn’t necessarily mean designers have to simulate all those nets, but it does mean they need to pay attention to best practice techniques like matching impedance, receiver termination, crosstalk, etc. It’s not just DDR interfaces and serial channels that need to be treated as high-speed signals anymore; it’s every net on every board. 

Most people would say, “Then use best practices and follow the manufacturer’s guidelines.” Which is fine as far as it goes, but in every design, there are probably a dozen design tradeoffs that require bending “the rules” and making a judgment call. You can’t follow the rules everywhere; it’s not practical.

But we have a chronic shortage of SI/PI experts, and it’s getting worse. Those experts are already tied up working on the hardest problems on the hardest boards. But if everything is high-speed and hard tradeoffs are common, that means the designers trying to make those tradeoffs are just making a judgment call and hoping for the best, with no analysis to back them up. The question becomes, “Can we provide tools that let a designer run basic (but useful) analyses by themselves, to increase their chance of success without bogging down the SI/PI experts?” That’s how we want to change the design process itself.

We’ve introduced a new capability in our 2.12 release called HyperLynx Apps. These are single-purpose tools that perform one analysis function, simply and automatically. They’re tools that a designer can use to compare design tradeoffs and decide which implementation is better, without requiring help from an SI/PI expert.

There are two types of HyperLynx apps. The first is a design app, which is meant to be run by a PCB designer or a hardware designer trying to make a layout decision. These apps run while you wait. You load the design, set the parameters, hit “run,” wait a few seconds, and a report pops up. Design apps are qualitative: You run the simulation with parameters that are representative of the design technology, but not device-specific. You’re not trying to qualify the design for fab-out; you’re trying to verify that the layout performs reasonably, and test changes to the layout to see if they make the design’s performance better or worse. 

The second type of HyperLynx app is a regression app, which performs a complete post-route verification of a set of signals, including layout extraction, EM modeling, analysis, and post-processing. A regression app produces a report that compares the design’s behavior against an applicable standard, showing which signals passed, which signals failed, and by how much. We call them regression apps because they can be run overnight while PCB layout is still in progress, instead of waiting until layout is complete. We’re all understand software regression testing: test gets run automatically during software development to determine which functions work. We see regression apps as that same concept applied to standards-based PCB design. If I’m designing a PCIe-5 channel, the electrical requirements for that channel to be considered compliant with the spec are well-established, so why not verify the serial channels in a layout on a regular basis during layout to ensure the design remains on-track?

Both design and regression apps can be run by PCB and hardware designers, so they can discover and resolve problems much sooner than if they had to wait for an SI expert to run analysis for them. Typically, SI/PI analysis is only run once layout is complete—when it’s harder to make design changes. If problems can be discovered and corrected earlier in the design cycle, everybody wins: designers spend less time waiting for SI/PI experts, SI/PI experts spend less time solving basic problems for others, and the PCB gets to market sooner with better quality.

Johnson: Are HyperLynx Apps running inside the normal layout environment?

Westerhoff: We’re leveraging the integrations that already exist between multiple PCB tools and HyperLynx. Customers are already using HyperLynx with all the mainstream PCB layout tools, so it made sense to start with that. 

Johnson: So, you’re plugged into the different PCB design flows to access the PCB database, but this is running as a standalone application? Which CAD tool is being used doesn’t matter?

Westerhoff: Correct. The apps run as a standalone application with their own GUI. The GUI itself is minimal, so the workflow is essentially: load the database, verify options, and press run.

Johnson: Can you give examples of what you called design apps?

Westerhoff: Good examples of a design app would be DC drop, loop inductance, and pulse response. Design apps are used to interactively analyze specific sections of a design for specific behaviors.

I recently spoke with Todd Westerhoff, product marketing manager for signal integrity software tools at Siemens. We discussed a new capability called HyperLynx Apps that offers a new take on traditional signal and power integrity analysis, and how that fits in with the Siemens plan to put SI and PI tools into the hands of more designers early in the design cycle.

Nolan Johnson: Todd, I understand there’s something new with HyperLynx.

Todd Westerhoff: That’s right. With HyperLynx our focus has always been about making signal and power integrity analysis accessible to a wider audience. Most SI/PI analysis today is performed by experts—people who do that analysis as their primary job. But there just aren’t enough SI/PI experts available to meet demand, and the problem is getting worse. We think it’s time to start looking at the problem differently.

I read a study from Semiconductor Engineering stating that the primary staffing problem electronics companies have is electrical engineers—they just can’t find enough of them, and it’s impacting project schedules. That study was pre-COVID, before the current exodus of experienced talent, and they were referring to general EEs, not SI/PI experts, who are much rarer. We recently searched LinkedIn for jobs relating to signal integrity and found over 2,000 jobs worldwide. Then we ran a more targeted search with just five companies with the acronym AMIGA—Apple, Microsoft, Intel, Google, and Amazon, and only in the United States. That focused search still listed 321 jobs­.

That means it’s a great time to be a signal integrity expert, but it’s terrible time to try to hire one. We’ve been talking about the “expert crunch” and how it hasn’t been getting any better for a while now; we think it’s time to think about how we can approach analysis differently. This requires a new vision for how high-speed systems should be designed and verified.

Johnson: Do you all believe the high-speed system design methodology needs to change?

Westerhoff: Yes, because we need to change the way we look at the problem. Let’s take a broad perspective: The classic definition of “high-speed” relates a signal’s edge rate to the electrical delay of the net. It defines the point at which you must pay attention to how you lay out that net. Simply put, if you have to pay attention to how you route it, it’s “high-speed.”

The challenge is that by today’s standards, everything is high speed. Using modern devices and typical board materials, the longest a net can be before it runs into “high-speed” issues is about one-quarter inch, and basically everything is longer than that. That doesn’t necessarily mean designers have to simulate all those nets, but it does mean they need to pay attention to best practice techniques like matching impedance, receiver termination, crosstalk, etc. It’s not just DDR interfaces and serial channels that need to be treated as high-speed signals anymore; it’s every net on every board. 

Most people would say, “Then use best practices and follow the manufacturer’s guidelines.” Which is fine as far as it goes, but in every design, there are probably a dozen design tradeoffs that require bending “the rules” and making a judgment call. You can’t follow the rules everywhere; it’s not practical.

But we have a chronic shortage of SI/PI experts, and it’s getting worse. Those experts are already tied up working on the hardest problems on the hardest boards. But if everything is high-speed and hard tradeoffs are common, that means the designers trying to make those tradeoffs are just making a judgment call and hoping for the best, with no analysis to back them up. The question becomes, “Can we provide tools that let a designer run basic (but useful) analyses by themselves, to increase their chance of success without bogging down the SI/PI experts?” That’s how we want to change the design process itself.

We’ve introduced a new capability in our 2.12 release called HyperLynx Apps. These are single-purpose tools that perform one analysis function, simply and automatically. They’re tools that a designer can use to compare design tradeoffs and decide which implementation is better, without requiring help from an SI/PI expert.

There are two types of HyperLynx apps. The first is a design app, which is meant to be run by a PCB designer or a hardware designer trying to make a layout decision. These apps run while you wait. You load the design, set the parameters, hit “run,” wait a few seconds, and a report pops up. Design apps are qualitative: You run the simulation with parameters that are representative of the design technology, but not device-specific. You’re not trying to qualify the design for fab-out; you’re trying to verify that the layout performs reasonably, and test changes to the layout to see if they make the design’s performance better or worse. 

The second type of HyperLynx app is a regression app, which performs a complete post-route verification of a set of signals, including layout extraction, EM modeling, analysis, and post-processing. A regression app produces a report that compares the design’s behavior against an applicable standard, showing which signals passed, which signals failed, and by how much. We call them regression apps because they can be run overnight while PCB layout is still in progress, instead of waiting until layout is complete. We’re all understand software regression testing: test gets run automatically during software development to determine which functions work. We see regression apps as that same concept applied to standards-based PCB design. If I’m designing a PCIe-5 channel, the electrical requirements for that channel to be considered compliant with the spec are well-established, so why not verify the serial channels in a layout on a regular basis during layout to ensure the design remains on-track?

Both design and regression apps can be run by PCB and hardware designers, so they can discover and resolve problems much sooner than if they had to wait for an SI expert to run analysis for them. Typically, SI/PI analysis is only run once layout is complete—when it’s harder to make design changes. If problems can be discovered and corrected earlier in the design cycle, everybody wins: designers spend less time waiting for SI/PI experts, SI/PI experts spend less time solving basic problems for others, and the PCB gets to market sooner with better quality.

Johnson: Are HyperLynx Apps running inside the normal layout environment?

Westerhoff: We’re leveraging the integrations that already exist between multiple PCB tools and HyperLynx. Customers are already using HyperLynx with all the mainstream PCB layout tools, so it made sense to start with that. 

Johnson: So, you’re plugged into the different PCB design flows to access the PCB database, but this is running as a standalone application? Which CAD tool is being used doesn’t matter?

Westerhoff: Correct. The apps run as a standalone application with their own GUI. The GUI itself is minimal, so the workflow is essentially: load the database, verify options, and press run.

Johnson: Can you give examples of what you called design apps?

Westerhoff: Good examples of a design app would be DC drop, loop inductance, and pulse response. Design apps are used to interactively analyze specific sections of a design for specific behaviors.

When we’re laying down power planes, we’re asking, “Do we have enough metal to carry the current needed, and will neckdowns cause problems due to excessive voltage drop?” The DC drop app will allow you to analyze and visualize current flow under steady state conditions, so you can quickly identify and correct potential problems.

When we’re designing an AC power delivery network (PDN), we’re placing decoupling capacitors, and we’re asking, “Do we have enough capacitors, with the right values, close enough to the devices they need to service?” The traditional approach to placing decoupling capacitors has often been called “sprinkle and pray,” which results in overdesign and higher manufacturing costs. Being able to determine how many capacitors are actually needed makes the process more reliable and frees valuable board space that would have been occupied by unnecessary capacitors.

Pulse response analysis considers a group of signals that should have nearly identical electrical characteristics to see if there are any outliers. This is first-order signal integrity; I don’t need the exact driver model; I just need a technology model with about the right impedance at about the right edge rate. That makes the setup and simulation process much simpler. I can quickly analyze a group of related signals (think DDR data or address bus) to see if anything stands out, then go from there.

Johnson: This is the “signal and power integrity for the average engineer” you’ve been talking about in past interviews?

Westerhoff: Right. It’s based on reframing the way we typically think about signal and power integrity. Typically, we’re told that signal integrity and power integrity need to be detailed, quantitative, and exact, down to the millivolt or picosecond. That results in a process that can only be performed by SI/PI experts. The analysis we perform with design apps is more of a qualitative approach. We’re running first-order analysis during layout to tune things as we lay them down, identifying and resolving obvious problems as we go. Remember, design apps aren’t trying to perform signoff analysis; we assume the normal signoff process still applies.

Regression apps are more what we typically consider as signal integrity because they’re specific and quantitative. They’re also different in that they are standards-based and focus on spec compliance instead of device-specific performance. It’s much easier to determine whether a channel is compliant with a spec because all you need is the layout database and which protocol you want to analyze it for; everything else is already known. Traditional serial channel analysis involves vendor IBIS-AMI models, which is a much more complicated and case-dependent proposition. Protocol compliance analysis is well-defined once you know the protocol, so it can be automated.

The extraction and electromagnetic modeling process for serial channel compliance is pretty complex, so this isn’t a “while you wait” process; it’s an automated, overnight run. Load the layout database at the end of the day, start the compliance app, and have a report ready for the next morning. That’s the workflow.

Setting up a regression app is more involved, so it can make sense to have an SI/PI expert set up the initial run and save that setup to a library. That makes sure that everything is configured correctly to ensure a correct final result. Once the setup is in the library, the designer can rerun the analysis as often as they need at the push of a button.

Johnson: How accurate are the results we’re talking about here? How well do HyperLynx Apps results compare to HyperLynx?

Westerhoff: Excellent question. As we said, signal and power integrity are traditionally all about accuracy. The important point here is that HyperLynx Apps are HyperLynx. We’ve just created a simpler front-end for specific tasks. We’re building on the infrastructure HyperLynx already has, so the accuracy and analytical capabilities are the same. In some cases, the app calls the automated flows that have existed in HyperLynx for some time now.

Johnson: What happens if a designer runs across a problem that they can’t resolve using the app?

Westerhoff: Good point. We’re giving PCB and hardware designers the ability to run analysis themselves, but the design problems can still be quite complex. They eventually will run into something that they can’t resolve, so then what? Remember that HyperLynx Apps use the same database and analytical methods as traditional HyperLynx. That means that when a designer runs analysis and gets stuck, the HyperLynx simulation setup and results already exist. An experienced user can open up the project with traditional HyperLynx and dig right in.

Johnson: The designer escalates the problem, so the SI/PI experts can take a look at it?

Westerhoff: Right, but the SI/PI experts get the problem handed to them on a silver platter, with a complete simulation setup and results available. It’s all ready to go.

Johnson: When will these HyperLynx Apps be available?

Westerhoff: We began shipping HyperLynx Apps with the 2.11 release this March. We’ve been working with select customers on this concept for a while, and we’ve just opened it up for general use.

Johnson: Thanks for speaking with me, Todd.

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